Audinate releases Dante IP Core for Xilinx FPGAs

[jabbr]

1 hour ago, vortecjr said:

You can't just add Dante to every device that has an FPGA in it. The PS Audio DS would likely need a new bridge with an FPGA on it.   

No I used that as an example of a DAC with the Spartan-6 — if it has Ethernet input and enough free cells then you could add Dante — of course the FPGA would need to be reprogrammed. I think Ayre may also use the Spartan 6 but depends on free cells.

[Miska]

9 hours ago, jabbr said:

No I used that as an example of a DAC with the Spartan-6 — if it has Ethernet input and enough free cells then you could add Dante — of course the FPGA would need to be reprogrammed. I think Ayre may also use the Spartan 6 but depends on free cells.

 

I think both are way too full already to have space for such functionality. Dante implementation is probably not among the smallest, probably containing MicroBlaze or some other MCU for the network protocol stack. Trying to do something like DHCP client as pure hardware is pointless.

 

[Miska]

23 hours ago, jabbr said:

Exactly! so putting an Ethernet frame(s) into a buffer — and splitting out the DSD into parallel I/O lines under control of an external clock is very very simple. No need for clocks in the GHz range — Ethernet can go in with a dedicated high speed I/O (eg GTX I think on Altera) — FPGAs used in 100gbe NICs. FPGA makes great IO machine .... math ... err depends.

 

But doing DSD1024 x 16 (saturates 1Gbe) is doable. 

 

Depends what you mean by doing "DSD1024 x16", for me it means doing DSP and delta-sigma modulation for 16 channels of DSD1024...   If you want to run my adaptive modulators at such rates, you'll need GHz clocks.

 

If you just mean shoveling ready-made data around, you are correct.

[jabbr]

44 minutes ago, Miska said:

 

Depends what you mean by doing "DSD1024 x16", for me it means doing DSP and delta-sigma modulation for 16 channels of DSD1024...   If you want to run my adaptive modulators at such rates, you'll need GHz clocks.

 

If you just mean shoveling ready-made data around, you are correct.

 

Here I mean accepting and deserialzing that amount of data. I’m saying that’s the limit of what 1gbe can handle, to go above that would require 10gbe. 

 

That may slso get close to saturate the internal ARM <-> FPGA channels at the lowest  end FPGAs.

 

The take home here is that handling these levels of IO and similar I assume for multichannel Dante/Ravenna can saturate a low end FPGA in and of itself not leaving much for filtering (perhaps). 

 

Interestingly the highest end “RF SoC” can do multichannel 5ish GHz ADC/DAC — these are for Radar/SDR/Cellular etc. They use some tricks to get the bandwidth higher than the clock rate — mostly parallelizing the problem. ... these chips aren’t cost effective for our purposes 

[Ralf11]

can I back you guys up for a nano-second and ask just what the gate arrays are used for in these applications?

[Miska]

6 hours ago, jabbr said:

Here I mean accepting and deserialzing that amount of data. I’m saying that’s the limit of what 1gbe can handle, to go above that The take home here is that handling these levels of IO and similar I assume for multichannel Dante/Ravenna can saturate a low end FPGA in and of itself not leaving much for filtering (perhaps). 

 

I don't think this IO bandwidth is problem in this. But just amount of logical blocks used by different functions vs available number of blocks on the FPGA. For example just MicroBlaze MCU alone would take quite a bunch of space.

 

For example the DSP algorithms in DirectStream likely take up so large portion of available blocks that there is hardly space left for something like Dante. This is not about speed, but about size of the functionality.

 

6 hours ago, jabbr said:

Interestingly the highest end “RF SoC” can do multichannel 5ish GHz ADC/DAC — these are for Radar/SDR/Cellular etc. They use some tricks to get the bandwidth higher than the clock rate — mostly parallelizing the problem. ... these chips aren’t cost effective for our purposes 

 

Not every algorithm can be parallelized though. That's also why GPUs cannot help on all things HQPlayer does.

 

[jabbr]

5 hours ago, Miska said:

I don't think this IO bandwidth is problem in this. But just amount of logical blocks used by different functions vs available number of blocks on the FPGA. For example just MicroBlaze MCU alone would take quite a bunch of space

 

It depends. e.g.: https://forums.xilinx.com/t5/Networking-and-Connectivity/PHY-transceiver-for-1Gig-Ethernet-connectivity/m-p/219619/highlight/true#M3164

 

Yes you could potentially redesign the board and add an external Ethernet PHY, or, as described, go with a higher-end FPGA which has builtin high speed IO channels (GTP/GTX) and then do the Ethernet PHY in IP. All depends on what you are starting with.

[Miska]

1 hour ago, jabbr said:

It depends. e.g.: https://forums.xilinx.com/t5/Networking-and-Connectivity/PHY-transceiver-for-1Gig-Ethernet-connectivity/m-p/219619/highlight/true#M3164

 

Yes you could potentially redesign the board and add an external Ethernet PHY, or, as described, go with a higher-end FPGA which has builtin high speed IO channels (GTP/GTX) and then do the Ethernet PHY in IP. All depends on what you are starting with.

 

Ehm, how is that related? Having something as simple as Ethernet PHY is not so much an issue. You can buy PHY as a separate purpose-built chip.

 

1 hour ago, jabbr said:

Yes you could potentially redesign the board and add an external Ethernet PHY, or, as described, go with a higher-end FPGA which has builtin high speed IO channels (GTP/GTX) and then do the Ethernet PHY in IP. All depends on what you are starting with.

 

Well, Spartan-6 is certainly not higher-end, it is low-end. But ethernet is not so much issues, than the higher level things needed, although ethernet MAC with checksumming offload and such would also take already some space. You certainly want full checksumming offload, zero-copy DMA and such for handling higher channel counts and rates if you use something as low performance as MicroBlaze as MCU. Entire IP protocol stack, PTP protocol, RTP/RTCP/RTSP protocols, DHCP client, etc, etc. All that actually makes up Dante. Ethernet and IP protocol stack are just fundamental basic ingredients that don't yet alone do anything useful.

 

[jabbr]

18 hours ago, Ralf11 said:

can I back you guys up for a nano-second and ask just what the gate arrays are used for in these applications?

 

Typically you’d have a board with digital gates present on different chips and connected various ways. In the 1980s, the DOD wanted a way to specify this hardware and a Hardware Definition Language — VHDL was developed. Similarly Verilog was developed as an alternate HDL. These languages not only specify the hardware but enable simulation if the hardware. 

 

Using VHDL or Verilog, a custom chip can be developed replacing the board (ASIC)

 

An FPGA is a chip that can be programmed using a compiled VHDL, and be reprogrammed.

 

Using VHDL you can specify arbitrary digital schematics for circuits including entire CPUs — the Microblaze is a CPU defined by VHDL.

 

So in this case the FPGA can include both an Ethernet PHY, FIFO, processor, as well as gates to deserialize and reclocking the bits into individual streams of DSD .

[jabbr]

6 hours ago, Miska said:

Ehm, how is that related? Having something as simple as Ethernet PHY is not so much an issue. You can buy PHY as a separate purpose-built chip.

The link referenced a discussion of what is needed to either use an external Ethernet PHY vs incorporate into the FPGA. Although external PHY are of course available they need to be incorporated and the interface tested. 

 

To the extent you are able to use an already developed module (SOM) the development work can be done in VHDL/Verilog — which may be easier — in all cases there are trade offs.

 

As a concrete example, if I wished to upgrade an input from 1Gbe to 10Gbe, it might be as simple as swapping a higher grade version of the same SoC /FPGA family, rather than design build and test an entirely new board with a new PHY.

[Ralf11]

34 minutes ago, jabbr said:

 

Typically you’d have a board with digital gates present on different chips and connected various ways. In the 1980s, the DOD wanted a way to specify this hardware and a Hardware Definition Language — VHDL was developed. Similarly Verilog was developed as an alternate HDL. These languages not only specify the hardware but enable simulation if the hardware. 

 

Using VHDL or Verilog, a custom chip can be developed replacing the board (ASIC)

 

An FPGA is a chip that can be programmed using a compiled VHDL, and be reprogrammed.

 

Using VHDL you can specify arbitrary digital schematics for circuits including entire CPUs — the Microblaze is a CPU defined by VHDL.

 

So in this case the FPGA can include both an Ethernet PHY, FIFO, processor, as well as gates to deserialize and reclocking the bits into individual streams of DSD .

 

Thanks.  I understand the first part of your answer - it was the last part I was after.

 

I am supposing that production runs are too small to make using an ASIC or even a dedicated design chip ....

 

Are there any noise or other problems involved in using FPGAs for audiophile purposes?

[Miska]

37 minutes ago, Ralf11 said:

Are there any noise or other problems involved in using FPGAs for audiophile purposes?

 

They are relatively power hungry compared to ASICs, or inefficient for CPU implementation. But they are often good replacement for cases where you would need lot of traditional chips like 74-series logics or similar. Depending on compilation result and used I/O pins and block allocation, signal propagation delays vary. So for signal consistency one may need to manually assign logic blocks that are near the I/O pins. For example going to neighboring pin is usually faster than going across the chip.

 

So just like board layout design, you also need to pay attention to on-chip layout design. But you cannot do hand-drawn optimizations like you can with ASIC or PCB design.

[jabbr]

6 hours ago, Ralf11 said:

Thanks.  I understand the first part of your answer - it was the last part I was after.

 

 

CPU provides memory buffer of bits. Application is to serialize as individual lanes of either DSD or PCM

 

Output pins:

 

BCLK

WCLK

DSD [1-16]

DSD_ENABLE

CLOCK_FAMILY

 

Consider implementing this using CPU?

Consider implementing using logic chips?

[Ralf11]

hmmm, sounds like you are the mercy of the manfs. on-chip layout design

 

and this market turns out to be dominated by 2 co.s

 

oh, well... I just buy boxes anyway ;]

[jabbr]

11 hours ago, Ralf11 said:

hmmm, sounds like you are the mercy of the manfs. on-chip layout design

 

I would let an expert like @marce discuss the trade offs of hand vs automated board layout with complex designs. 

 

Regarding FPGA layout, there are many complexities, including specialized IO pins, clock domains etc and the topic can get complex however needs to be considered something like functional programming where the layout is guided by sets of constraints. Constraints include necessary delays for clock latching as well as limits. These limits constrain the path lengths within the chip. 

[marce]

LOL dont use any automated tools these days, placement is the main skill with layout, this is especially true with analogue designs, digital can be more forgiving until you get to high speed. Get the placement right is the first and most important factor... Then routing, all manual these days, don't know any designers personally that use autorouter's (and I know a few:))... As Jabbr has said when you get onto high speed digital you end up with constraints... We use this:

https://www.zuken.com/en/products/pcb-design/cadstar/products/schematic-capture/constraint-browser

You get the basic routing down (leaving room for length matching if required) then its back and forth getting all the constraints fulfilled, that is the fun part, especially a DDR interface with 2 or more memory devices (DIMMs or seperate memory IC's) as is often the case with FPGA layout. The constraints guide you with on screen traffic lights, the fun is when you have multiple skew groups so changing one often means you have to go back and change others... it can take days. Then you check everything back in the constraint manager and depending on how much the punter wants to pay and play we will do simulations of the actual layout to check everything for signal integrity etc.

Here is an interesting FPGA design, about 4,500 connections, 2,000 pads. The smaller pic shows the DDR differential clock, all the other squiggly bits (as I call them...) are the data bus lanes, address and control signals. This is an extreme design, I will try and find some pics of routers and switches as they tend to be far simpler though...

[Miska]

2 hours ago, marce said:

Here is an interesting FPGA design, about 4,500 connections, 2,000 pads. The smaller pic shows the DDR differential clock, all the other squiggly bits (as I call them...) are the data bus lanes, address and control signals. This is an extreme design, I will try and find some pics of routers and switches as they tend to be far simpler though...

 

I've done similar stuff for radar things. Board layout was one PITA, but even more so was to make the insides and outside of the FPGA match requirements. Since it's neither alone, but the combination. And FPGA is not as flexible as the board design, it has it's hard constraints... (like, "ahh shit, I need to swap these two pins to make the FPGA work, damn, I need to redesign half of the board too") But that was still relatively small effort compared to the software.

 

This year, HQPlayer is 20 years old and my company is 10 years...

[marce]

2 hours ago, Miska said:

 

I've done similar stuff for radar things. Board layout was one PITA, but even more so was to make the insides and outside of the FPGA match requirements. Since it's neither alone, but the combination. And FPGA is not as flexible as the board design, it has it's hard constraints... (like, "ahh shit, I need to swap these two pins to make the FPGA work, damn, I need to redesign half of the board too") But that was still relatively small effort compared to the software.

 

This year, HQPlayer is 20 years old and my company is 10 years...

 

 

[jabbr]

On 1/9/2018 at 11:37 AM, marce said:

This is an extreme design, I will try and find some pics of routers and switches as they tend to be far simpler though...

I thought this was a new iTunes visualizer playing Pink Floyd — maybe for HQPlayer’s 20 year anniversary we could get a 3D visualizer? I mean with the NVidia GPUs we could have the concert projected holographically, and with the room correction kernel, the soundstage could be adjusted to match the hologram? Just a thought @Miska

[ferenc]

6 hours ago, jabbr said:

I thought this was a new iTunes visualizer playing Pink Floyd — maybe for HQPlayer’s 20 year anniversary we could get a 3D visualizer? I mean with the NVidia GPUs we could have the concert projected holographically, and with the room correction kernel, the soundstage could be adjusted to match the hologram? Just a thought @Miska

 

Actually on a project meeting to deal with some AI and machine learning features for video (depth processing as such and AI and depth image helped keying) and potentially for stage presentation, we were talking about exactly this .

 

(off: we can do real-time depth processed professional quality keying (with a camera accessory called zKey™ and 12 core i9 CPU) where we do not need green or blue screen or solid color background at all in the background)

 

 

[Miska]

...I did some 3D volumetric processing for sonar systems (passive sonar input) some 10+ years ago. For audio playback that is even older stuff.

 

Now that HQPlayer Embedded supports also realtime audio inputs, it could do some other interesting things too...

[Superdad]

On 1/6/2018 at 1:57 AM, Miska said:

Someone once asked me what would it take to run HQPlayer algorithms on FPGA and after calculations I ended up pretty much at the biggest and fastest Virtex models and still couldn't be sure if it'll fit and work. After that they weren't interested anymore...

 

I'm pretty sure it was me who asked.  At the time we were considering an Altera Cyclone VE with 301K logic elements and 114K LABs. 484 BGA package for $228.  Not for a budget DAC, that's for sure.

 

 

On 1/4/2018 at 11:09 PM, ferenc said:

So Ravenna is better to be integrated inside. I do not know what is the OEM requirement to get their board, it is probably lot more expensive to get and to implement than getting the Dante Core and its FPGA solution. 

 

Actually Merging is making ZMAN quite reasonable and accessible.  We are under NDA so I can't disclose pricing or the tech details, but they are not unattractive.

The most compelling aspect (versus going it alone along the lines of what @jabbr is doing)-- is as have always said would be most important for a consumer product--is that Merging is providing (and supporting) their VSC s/w for the major OS platforms.  For designers who don't want to become software companies this is important.

[jabbr]

22 hours ago, Superdad said:

Actually Merging is making ZMAN quite reasonable and accessible.  We are under NDA so I can't disclose pricing or the tech details, but they are not unattractive.

The most compelling aspect (versus going it alone along the lines of what @jabbr is doing)-- is as have always said would be most important for a consumer product--is that Merging is providing (and supporting) their VSC s/w for the major OS platforms.  For designers who don't want to become software companies this is important.

 

Well to be entirely clear ZMAN/FPGA has both programmable software and hardware so what you they are doing with Ravenna is completely different and than what I am doing with essentially the same SoC — Zynq — when you outsource the implementation this is identical to outsourcing your USB implementation  to an XMOS chip — devil is always in the details. 

 

I suspect ZMAN will allow you to customize the IP but ... now you are essentially a software company.

[ferenc]

https://audinate.com/products/devices/dante-avio?utm_campaign=AVIOLaunch&utm_source=hs_email&utm_medium=email&utm_content=60118988&_hsenc=p2ANqtz-_jyuu6sWzDS3-YlWyky8ZCK-w1SrdlO5g7SUURBAB3preVSgK-a9tbjW9spAO6oiolsj77MnSdcncRWItwEvDv6AI8_A&_hsmi=60119637

 

From 129 USD. 

 

Dante AVIO Adapters let you use your favorite legacy audio gear with any Dante-connected system, delivering the interoperability, performance and scalability that only networking can bring. Cost effective, compact and built for the road, Dante AVIO adapters bring the modern connectivity that every audio pro needs in their toolbox. 

Analog Input  Analog Output AES3 USB 

 

Analog Inputs

 

Dante AVIO Analog Inputs let you use analog audio line-level source gear you already own to feed any Dante-connected system. Don’t abandon trusted mixing consoles, wireless mics and other analog sources - adapt them to the world of audio networking with Dante AVIO. Available in 1- and 2-channel versions.

 

• Connect legacy mixers and consoles to a Dante network
• Patch DSPs, analog compressors and equalizers into a Dante system using a combination of Dante AVIO Input and Output adapters
• Connect stage DI boxes and keyboard instruments directly to a Dante network

 

 

Analog Outputs

 

Dante AVIO Analog Outputs let you drive analog line-level products you already own from any Dante-connected system. Bring your amplifiers, powered speakers and more to the world of audio networking with Dante AVIO. Available in 1- and 2-channel versions.

 

• Send audio to analog power amplifiers and powered speakers over a Dante audio network
• Patch DSPs, analog compressors and equalizers into a Dante system using a combination of Dante AVIO Input and Output adapters
• Create easy drop-points for connecting overflow areas to a Dante network

 

 

AES3

 

The Dante AVIO AES3/EBU Adapter lets you use your favorite digital audio gear on a Dante audio network. Don’t abandon great AES3-connected amplifiers, DSPs and mic preamps - adapt them to the world of audio networking with Dante AVIO.

 

• Send audio to analog power amplifiers and powered speakers over a Dante audio network
• Patch DSPs, analog compressors and equalizers into a Dante system using a combination of Dante AVIO Input and Output adapters
• Create easy drop-points for connecting cry rooms and overflow areas to a Dante network

 

 

USB

 

The Dante AVIO USB Adapter lets you connect any computer to a Dante audio network with zero software installation, and can be used with any audio application for playout or recording. Ideal for conference rooms and presentation events.

 

• Easy audio drop-point for laptops in conference settings, no need to reconfigure your Dante network for different computers
• Record or playout 2-channel audio from any PC or Mac with no additional software at all
• Connect mobile devices to a Dante network (with USB adapters)

 

 

Specifications

Four types of Dante AVIO Adapters will be available, including one- and two-channel versions of the analog input and analog output adapters.

 

Feature Matrix	Analog Input 1 Ch	Analog Input 2 Ch	Analog Output 1 Ch	Analog Output 2 Ch	USB I/O 2 In 2 Out	AES3 I/O 2 In 2 Out
Signal level	Balanced: +18dBu sine => 0dBFS		Balanced: +24 / +4 / +2.4 / -0.5 / -7.6 dBu @ 0dBFS		-	-
Frequency Response	20Hz to 20kHz (-/+0.5dB)		20Hz to 20kHz (-/+0.5dB)		-	-
Impedance	Input: 20k Ohm balanced or 10k Ohm unbalanced		Output: 150 Ohm balanced or 75 Ohm unbalanced		-	110 Ohm bal­anced
Dynamic Range	> 100dB (unweighted) @ +18dBu		> 100dB		-	-
Signal to Noise Ratio	> 100 dB (unweighted) @ +18dBu		> 100dB		-	> 135dB (un­weighted)
Total Harmonic Distortion	< 0.01% at +4dBu		< 0.01% @ +4dBu		-	-
Channel Separation	-	> 100dB	-	> 90dB	-	-
Channel Matching	-	< 0.25dB	-	< 0.4dB @ 1kHz	-	-
Connectors	RJ45 & 1 x XLR female	RJ45 & 2 x XLR female	RJ45 & 1 XLR male	RJ45 & 2 XLR male	RJ45 & USB Type A	RJ45, 1 XLR male, 1 XLR female
Power	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE or USB	Class 1 802.3af PoE
Asyn­chronous Sample Rate Conversion	-		-		-	Yes
Sample Rates	44.1, 48, 96 kHz		44.1, 48, 96 kHz		48 kHz	44.1, 48, 96 kHz
Bit Depths	16, 24, 32		16, 24, 32		24	16, 24, 32
Audio Transport Formats	Dante Audio over IP, AES67 RTP		Dante Audio over IP, AES67 RTP		Dante Audio over IP, AES67 RTP	Dante Audio over IP, AES67 RTP
USB	-		-		USB 2 Full Speed Class 1 Audio	-
Part Number	ADP-DAI- AU-1X0	ADP-DAI- AU-2X0	ADP-DAO- AU-0X1	ADP-DAO- AU-0X2	ADP-USB-   AU-2X2	ADP-AES3- AU-2X2

[Miska]

6 hours ago, ferenc said:

 

Feature Matrix	Analog Input 1 Ch	Analog Input 2 Ch	Analog Output 1 Ch	Analog Output 2 Ch	USB I/O 2 In 2 Out	AES3 I/O 2 In 2 Out
Signal level	Balanced: +18dBu sine => 0dBFS		Balanced: +24 / +4 / +2.4 / -0.5 / -7.6 dBu @ 0dBFS		-	-
Frequency Response	20Hz to 20kHz (-/+0.5dB)		20Hz to 20kHz (-/+0.5dB)		-	-
Impedance	Input: 20k Ohm balanced or 10k Ohm unbalanced		Output: 150 Ohm balanced or 75 Ohm unbalanced		-	110 Ohm bal­anced
Dynamic Range	> 100dB (unweighted) @ +18dBu		> 100dB		-	-
Signal to Noise Ratio	> 100 dB (unweighted) @ +18dBu		> 100dB		-	> 135dB (un­weighted)
Total Harmonic Distortion	< 0.01% at +4dBu		< 0.01% @ +4dBu		-	-
Channel Separation	-	> 100dB	-	> 90dB	-	-
Channel Matching	-	< 0.25dB	-	< 0.4dB @ 1kHz	-	-
Connectors	RJ45 & 1 x XLR female	RJ45 & 2 x XLR female	RJ45 & 1 XLR male	RJ45 & 2 XLR male	RJ45 & USB Type A	RJ45, 1 XLR male, 1 XLR female
Power	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE or USB	Class 1 802.3af PoE
Asyn­chronous Sample Rate Conversion	-		-		-	Yes
Sample Rates	44.1, 48, 96 kHz		44.1, 48, 96 kHz		48 kHz	44.1, 48, 96 kHz
Bit Depths	16, 24, 32		16, 24, 32		24	16, 24, 32
Audio Transport Formats	Dante Audio over IP, AES67 RTP		Dante Audio over IP, AES67 RTP		Dante Audio over IP, AES67 RTP	Dante Audio over IP, AES67 RTP
USB	-		-		USB 2 Full Speed Class 1 Audio	-
Part Number	ADP-DAI- AU-1X0	ADP-DAI- AU-2X0	ADP-DAO- AU-0X1	ADP-DAO- AU-0X2	ADP-USB-   AU-2X2	ADP-AES3- AU-2X2

 

Hmmh, why are all those dongles limited to 96 kHz? And why is the USB dongle fixed to 48 kHz?