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The DSC1 DAC as a way to understand how a simple DSD DAC actually works

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jabbr   
3 hours ago, Miska said:

 

Analog FIR... ;)

 

Since there are 32 elements, there are 33 different possible output levels. The shift registers essentially create a scrambled unary coded value (as opposed to binary coded with PCM), sometimes called "thermometer code". This is how most SDM converters work (for example ESS Sabre, which has 64 elements). Compared to R2R ladder, in this type of converter, accuracy of the resistors don't affect conversion accuracy, only filter's frequency response. Every bit goes through every element once and every bit is converted 32 times.

 

Since every new sample has only 1/32th contribution to the converted value, it has filtering effect and thus reduces the slew rate I/V section is seeing which makes it easier to create good I/V and analog filter stages - lower level high frequency content. So the maximum sample-to-sample voltage step after I/V is 1/32th of the full range.

 

Using equal weighting for each element provides best possible jitter rejection but less filtering effect.

 

Hybrid :) 

 

In this FIR design, the "thermometer code" would often be followed by a summation block to convert to binary (PCM encoding) if one wanted to keep this in the digital domain (and minimize bit width) The exact point of D/A conversion occurs when the 32 lines which carry the digital average (thermometer encoded) are summed using the resistor network and become analog current.

 

So perhaps we don't need to use RF jFets in the I-V converter after all ;) SPICE simulation suggests that bandwidth limitation occurs as a result of the input capacitance of the jFet. By using parallel jFets we can keep within the linear current range (improving distortion) and reduce noise, and by cascoding, reduce the effective input capacitance. A disadvantage of using RF jFets is that they can tend to oscillate if the layout is careful etc. -- kind of like the accelerator on a Ferrari :) 

 

The advantage of a discrete I-V would be that very specific circuit parameters can be tweaked.

 

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Miska   
10 hours ago, jabbr said:

In this FIR design, the "thermometer code" would often be followed by a summation block to convert to binary (PCM encoding)

 

This scrambled unary coding has many advantages over binary coding and that is the reason why it is so much used these days in converters. It also means that you need to deal with low number of levels. Creating even 16-bit PCM DAC using similar technique would be pretty impractical, although theoretically possible! :D

 

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jabbr   

An interesting question will be whether DSD1024 will be better, worse, or the same as DSD512 after upsampling. At some point the increased close-in phase error of the 45 Mhz clock, being worse (laws of physics) than an equivalent 22 Mhz clock will increase noise rather than improve.

 

I had predicted that DSD512 would be equivalent to DSD256 for this reason but many people hear DSD512 as being better (the problem is, however, that you need to use different clocks, and not simply compare DSD256 vs DSD512 on the same DAC because its the master clock that determines, not the clock that is derived by division.

Edited by jabbr

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mansr   
33 minutes ago, Miska said:

This scrambled unary coding has many advantages over binary coding and that is the reason why it is so much used these days in converters.

Dynamic element matching is another name for this.

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Miska   
5 minutes ago, jabbr said:

An interesting question will be whether DSD1024 will be better, worse, or the same as DSD512 after upsampling. At some point the increased close-in phase error of the 45 Mhz clock, being worse (laws of physics) than an equivalent 22 Mhz clock will increase noise rather than improve.

 

I had predicted that DSD512 would be equivalent to DSD256 for this reason but many people hear DSD512 as being better (the problem is, however, that you need to use different clocks, and not simply compare DSD256 vs DSD512 on the same DAC because its the master clock that determines, not the clock that is derived by division.

 

From objective point of view, the improvement with DSD512 on DACs like DSC1 or T+A DAC8 DSD is that the amount of ultrasonic noise passing through gets reduced quite significantly. At DSD512, DSC1 gives practically flat noise floor. From audio bandwidth point of view, DSD512 should be already enough, and those 22/24 MHz clocks have pretty good phase noise performance, at least compared to 100 MHz clocks typically used with ESS Sabre...

 

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Miska   
3 minutes ago, mansr said:

Dynamic element matching is another name for this.

 

Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator.

 

But even without considering the conversion element part, it has advantages in digital domain. Scrambled unary presentation can have multiple representations for the same value, while binary has only one.

 

For example binary:

01 -> value 1

10 -> value 2

 

Same in scrambled unary:

0001 -> value 1

0010 -> value 1

0100 -> value 1

1000 -> value 1

1001 -> value 2

0110 -> value 2

1010 -> value 2

0101 -> value 2

1100 -> value 2

0011 -> value 2

 

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jtwrace   
49 minutes ago, Miska said:

 

From objective point of view, the improvement with DSD512 on DACs like DSC1 or T+A DAC8 DSD is that the amount of ultrasonic noise passing through gets reduced quite significantly. At DSD512, DSC1 gives practically flat noise floor. From audio bandwidth point of view, DSD512 should be already enough, and those 22/24 MHz clocks have pretty good phase noise performance, at least compared to 100 MHz clocks typically used with ESS Sabre...

 

Is there still any advantage of using your dac with Roon but not HQP?  

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Miska   
14 minutes ago, jtwrace said:

Is there still any advantage of using your dac with Roon but not HQP?  

 

You can use it with anything that can spit out DSD, as long as you use at least DSD128. Don't try to run it at DSD64, you'd get poor results.

 

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jtwrace   
Just now, Miska said:

 

You can use it with anything that can spit out DSD, as long as you use at least DSD128. Don't try to run it at DSD64, you'd get poor results.

 

Is there a simple PDF of what's required to DIY it?  Do you sell assembled boards for the lazy?  Measurements?  

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Jud   
26 minutes ago, jtwrace said:

Is there a simple PDF of what's required to DIY it?  Do you sell assembled boards for the lazy?  Measurements?  

 

Re the first two, schematics and no.  I'll leave the last to someone who knows.

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jabbr   
13 hours ago, Miska said:

 

Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator.

 

But even without considering the conversion element part, it has advantages in digital domain. Scrambled unary presentation can have multiple representations for the same value, while binary has only one.

 

For example binary:

01 -> value 1

10 -> value 2

 

Same in scrambled unary:

0001 -> value 1

0010 -> value 1

0100 -> value 1

1000 -> value 1

1001 -> value 2

0110 -> value 2

1010 -> value 2

0101 -> value 2

1100 -> value 2

0011 -> value 2

 

 

My (admittedly limited) understanding of DEM is that these multiple representations can be used to map depending on say a resistor value which may vary, and again for example, with an R2R ladder with more bits than appropriate for the accuracy level of the resistors, and in which non-monotonic transitions can occur, than DEM can be used to linearize or improve the accuracy of the R2R by selecting certain of the scrambled codes. (mapping the scrambled codes in order to linearize)

 

In the DSC1, is it correct that this is not needed? Because the running average always averages across the 32 resistors? ... otherwise, oh well I guess 32 bit LUTS are possible ... are you waiting for dual ported BRAM prices to come down for DSC2? :)

 

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jabbr   

Perhaps another use for DEM would be in a balanced DSC1 to linearize differences in the analogue electronics on the (+) and (-) sides. Probably easier to use trimmer pots ;)

 

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Jud   
Just now, shadowlight said:

 

If you search ebay for DSC1 you will find couple of users selling assembled boards.

 

Yes, but it's quite difficult to tell what those actually are.

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4est   
4 hours ago, jabbr said:

They look like they have output transformers ;) 

There are two versions and different kits- soldered, un soldered ect. One version akin to the original, and a second balanced version- kits with 1:1 transformers and sans transformers. I soldered mine and use my TVC as the transformer. It works great!

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4est   
1 minute ago, jabbr said:

Care to post a schematic?

What schematic?  :(  I bought mine bare board with labeled parts before there were assembled ones available. It was only about $50 with everything but transformers and I gave it a shot. No regrets. I question the inexpensive transformers, you don't get much for $20. The rest of it is solid, subjectively functioning pretty well.

 

You asked before about the circuit, but there is no schematic for the balanced one. Those parts are minuscule and a lil different than Miska's choices. I have a better scope now, and maybe I can read them. Let me know and I'll take a look.

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jabbr   
16 hours ago, 4est said:

What schematic?  :(  I bought mine bare board with labeled parts before there were assembled ones available. It was only about $50 with everything but transformers and I gave it a shot. No regrets. I question the inexpensive transformers, you don't get much for $20. The rest of it is solid, subjectively functioning pretty well.

 

You asked before about the circuit, but there is no schematic for the balanced one. Those parts are minuscule and a lil different than Miska's choices. I have a better scope now, and maybe I can read them. Let me know and I'll take a look.

 

Ok I thought perhaps they gave a bill of materials and schematic so you'd know what you were soldering where.

 

Balancing a single bit SDM stream is easy using a D-Flop which outputs + and -. Regarding digital switching noise, if both sides have very precise phase, then theoretically the switching signals will cancel. Changes in current will balance eachother. One issue, however, is when the signals arrive at different times to the chips. This can be caused by unequal trace path lengths and impedances. PCB routing can be important in this situation.

 

Does this make a difference? Well we talk about so-called "femtosecond" clocks. Signals travel down a one foot PCB trace in 1 - 2 nanoseconds -- so if the trace lengths are unequal that's a lot of femtoseconds ;) Vias also insert uncertainty. Another issue is clock distribution -- when a trace is fanned out this causes reflections (and phase error). A clock distribution chip reduces that (along with trace termination).

 

I've thought it amusing that many folks get caught up with using the latest and greatest "femtosecond" or "atomic" clock without a care in the world about how the DAC circuit actually works... now I'd be fairly certain that vendors such as ESS (and any large chip manufacturer) spend a fair amount of resources modeling trace delay and fan-out etc. -- particularly when they work at 100Mhz. For Ghz applications its absolutely essential.

 

Anyways when I think about folks "upgrading" a cheap circuit with an unknown design by using the worlds greatest and most accurate clock -- which costs waay more than the circuit its being applied to, my brain goes into a fog...

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