To DSD or not to DSD?

[Miska]

It would be cool if there was a way to select a different sampling rate for 44.1kHz- and 48kHz-based PCM files. I believe that's how most DACs operate internally, that is, they oversample 44.1kHz PCM files 128X to 5.6MHz DSD, and 48kHz to 6.1MHz DSD. Some DSD DACs (e.g. Playback Designs, Geek 1000, or iDSD) could take advantage of this feature as they accept both 5.6 and 6.1MHz DSD input rates...

 

But...why?

 

I can understand they do it internally that way because they don't have enough processing power for anything else.

 

Lot of DACs use ugly things like sample-and-hold internally to go above 8x oversampling ratios.

[Hiro]

But...why?

 

I can understand they do it internally that way because they don't have enough processing power for anything else.

 

Isn't such upsampling algorithm more straightforward? When upsampling, say a 48kHz file to 5.6MHz you have to do some extra math on the signal, you could otherwise avoid with an algorithm allowing for simpler 128 x 48kHz (6.1MHz) upsampling.

[Miska]

Isn't such upsampling algorithm more straightforward? When upsampling, say a 48kHz file to 5.6MHz you have to do some extra math on the signal, you could otherwise avoid with an algorithm allowing for simpler 128 x 48kHz (6.1MHz) upsampling.

 

"More straightforward" is not really straightforward, because the straightforward'ness depends on point of view... In fact, for same filter, the algorithm that is capable of any ratio is faster/more efficient than the one that can do only simple ratios... Certain algorithms and filters are useful only for those simple ratios, and for those cases HQPlayer automatically restricts available output rates to the possible subset.

 

You can manually select the output rate when starting playback, from that point on output is constant. It's the same for PCM upsampling too. There is some minimal support for switching the output rate on demand for the cases where that is needed (for example when rate conversion is disabled).

[Miska]

As an example here's oversampling using poly-sinc-mp 0 - 22.05 kHz sine sweep from 44.1/24 to 6144/32 (TPDF dithered). As we can see, stop-band attenuation is over 180 dB throughout.

 

[Bunpei]

Hi, Miska!

 

May I ask you the naming of your discrete DSD to analog converter, "Direct 1-bit, 33-level conveter”？

For me, the converter looks like an analog FIR filter with 32 taps of uniform co-efficient implemented with shift registers.

In this case, "Direct 1-bit, 32 tap converter" may describe the board well.

 

On the other hand, if a digital signal is given in a form of 32 bit thermometer coding and

converted in synchronizing a kind of word clock, it should be called as a "33-level converter".

 

What kind of DSD signal is applied to this converter actually?

[Miska]

May I ask you the naming of your discrete DSD to analog converter, "Direct 1-bit, 33-level conveter” For me, the converter looks like an analog FIR filter with 32 taps of uniform co-efficient implemented with shift registers. In this case, "Direct 1-bit, 32 tap converter" may describe the board well.

 

Yes, that is also correct way to call it. It's a combination of comb (CIC) filter and sallen-key filter, where corner frequency of the former depends on sampling rate and latter one uses fixed corner frequency.

 

However, it is this way in this particular design for demonstration purposes since it is in some ways similar with many of the existing multi-level delta-sigma DAC chips, in practice it has 32 1-bit converters in parallel. How the bits are fed to the equally weighted elements is another thing. In this case, scrambling (or dynamic element matching) is implemented using shift register. It is demonstrating how to create a bit-perfect multi-level converter from 1-bit source stream. Being this way, it has unique property of being able to adapt by just replacing the shift registers with different function it could create various different mappings to source data. Since log2(33)=5.0444 it could be also used with anything from 1-bit SDM source to 5-bit SDM source.

 

I could easily replace the 1-bit DSD input with custom 32-bit parallel input and then instead of shift registers I could do different kinds of tricks in the software...

 

I specifically wanted to avoid any FPGAs or similar where you would have to study the digital logic and conversion/analog domain separately. Now everything is visible at a glance. Make it balanced output and it would have equal conversion elements to Sabre. Now it already has more than dCS Debussy (?).

 

So it is specifically demonstrating how to create a bit-perfect DSD converter using multi-level delta-sigma DAC and achieve practically flat noise floor without ultrasonic noise bumps while doing so. Thus the difference between multi-level SDM and DSD doesn't really exist. But this converter won't convert PCM. It is also trying to emphasize the difference between multi-level SDM and PCM.

 

I will make some more variations to show how this design can be improved further specifically for DSD case and turn it to balanced design, but this one is due to above reasons this particular way (and to make the DSC1 design as simple as possible but not any simpler).

 

Hopefully this design clarifies that you don't need to convert to "PCM" or anything like that to fully utilize a multi-bit/multi-level SDM DAC for DSD. There is no two's complement (PCM) representation anywhere. And also that such DSD DAC can be created in a "discrete" way with reasonable price and accuracy compared to similarly performing discrete R2R. Plus that there doesn't have to be any ultrasonic noise bumps compared to bunch of multi-bit SDMs out there that really doesn't make so much technical difference.

 

("SAC" as DSD-to-PCM noise filter in HQPlayer 3.3.2 quite closely simulates this converter sampled with "perfect" PCM ADC)

 

On the other hand, if a digital signal is given in a form of 32 bit thermometer coding and

converted in synchronizing a kind of word clock, it should be called as a "33-level converter".

 

It is still 33-level converter, because at every conversion step there are 33 possible different output levels. Every 1-bit input triggers a new conversion. It IS actually using thermometer coding, but it just has property certain type of thermometer code construction.

 

What kind of DSD signal is applied to this converter actually?

 

I have optimized the design for my seventh order modulators in HQPlayer running at minimum at 5.6 MHz, but preferably at 11.3. This maximizes the performance. Amanero Combo384 USB board was chosen specifically due to support for rates up to 24.576 MHz.

 

Based on initial measurements it performs as expected. Ultrasonic noise is practically flat up to 350 kHz and then drops below the analog noise floor from.

 

The difference this has to the traditional DAC chip designs, is that you don't have to count transistors. You already have huge pile of those in a computer and not going to see similar number in any DAC chip any time soon.

 

P.S. The shift register can operate up to 130 MHz speeds, but there's no such DSD USB input adapter available.

[Bunpei]

P.S. The shift register can operate up to 130 MHz speeds, but there's no such DSD USB input adapter available.

 

Hi, Miska!

I appreciated your very detailed explanation! I think I have understood your "design philosophy" well.

 

As you can achieve all the signal processing in a main CPU(s) domain, what you require for audio hardware might be a transparent & high speed digital output mechanism and an array of digital switches.

Why don't you use a PCI Express bus based digital switches with FIFO which is mapped as a memory chunk? Of course, in this case, you need a galvanic isolation and an asynchronous output ticked by high performance oscillators of audio frequencies.

 

You would implement even a DEM in your software processing!

[testererr]

This design uses a first order DEM, right?

How hard is it to implement a 2nd-order DEM, like in this paper?

The graph in paper shows it behaving very well at oversampling ratios of 100+.

http://www.iet.ntnu.no/courses/fe8114/files/Report_audiodac.pdf

[Miska]

This design uses a first order DEM, right?

How hard is it to implement a 2nd-order DEM, like in this paper?

The graph in paper shows it behaving very well at oversampling ratios of 100+.

http://www.iet.ntnu.no/courses/fe8114/files/Report_audiodac.pdf

 

Given that it is used in this particular way for 1-bit input streams, it cannot be directly compared to those DEM used for multi-bit inputs. Since the input is 1-bit, there's not really any error to shape in the DEM. I will later on publish a modification to further enhance the performance, but it will also make the design less generic. In the current form it is fairly generic for different kinds of configurations and closest match to on-chip equivalents.

 

More there are input levels, more there is need for DEM. With just two input levels the need for DEM is minimum. This is analog 2-level to 33-level conversion...

[Hiro]

Since log2(33)=5.0444 it could be also used with anything from 1-bit SDM source to 5-bit SDM source.

 

Interesting. I believe it's an industry first!

 

It would be neat if DAC chip manufacturers offered such a capability as well. That way we could do away with upsampling algorithms implemented on resource-constrained chips, and use vastly more powerful computers to feed them with 5-bit DSD directly.

 

Not sure why this hasn't been done yet. It should be a standard feature on each and every SDM DAC chip.

[Hiro]

Interestingly enough, manufacturers like TI/BB or ARDA allow for tapping into 6-bit delta sigma stream generated by delta sigma ADCs to the great benefit of those who have the know-how to perform superior outboard processing on the stream, as evidenced here.

[mlgrado]

Sometimes I wonder if these multi bit delta sigma, sigma DPCM or whatever you want to call it DAC's are the best solution for recording DSD.

 

I would think true 1 bit ADC's like the Grimm AD1 are the way to go, because there is no extra conversion step. Going from 5 or 6 bit sigma DPCM to 1 bit requires re-modulation and perhaps filtering. So, as I said, an extra processing step.

 

Too bad we can't store and playback the raw output from one of these multi-bit DS converters. Now THAT is something I would be interested in hearing. Pure multi-bit DS without all the intermediate filtering and re-modulations.

 

Hmmm.. furthermore, if we could just have the raw multi-bit DS stream, it could even be kind of format agnostic. The end user could convert it to whatever suits his fancy. Keep it native, re-modulate to 1 bit DSD, decimate to DXD... whatever.

 

Ah... well, done dreaming now

 

 

 

Interestingly enough, manufacturers like TI/BB or ARDA allow for tapping into 6-bit delta sigma stream generated by delta sigma ADCs to the great benefit of those who have the know-how to perform superior outboard processing on the stream, as evidenced here.

[Miska]

Sometimes I wonder if these multi bit delta sigma, sigma DPCM or whatever you want to call it DAC's are the best solution for recording DSD.

 

I would think true 1 bit ADC's like the Grimm AD1 are the way to go, because there is no extra conversion step.

 

Channel Classics uses Grimm. But more inexpensive options are the DSD recorders based on PCM4202/PCM4204 chip like Korg and TASCAM. It is true 1-bit ADC capable of up to 6.1 MHz DSD and it's pretty good dithered one. I've been using it in my own DSD A/D/A converter (DAC side is CS4398 in DirectDSD mode).

 

Too bad we can't store and playback the raw output from one of these multi-bit DS converters. Now THAT is something I would be interested in hearing. Pure multi-bit DS without all the intermediate filtering and re-modulations.

 

Nothing prevents building such recorder both PCM4222 and the Arda chip have raw multi-bit modulator output.

[Hiro]

I would think true 1 bit ADC's like the Grimm AD1 are the way to go, because there is no extra conversion step. Going from 5 or 6 bit sigma DPCM to 1 bit requires re-modulation and perhaps filtering. So, as I said, an extra processing step.

 

Personally, I am an advocate of designing DSD ADCs (be it 1-bit or few-bit DSD) from the ground up with no off-the-shelf chips, especially when we are talking about "studio-grade" equipment. Furthermore, I strongly believe that to really push things forward with DSD and the now available higher DSD rates, we are going to need a discrete DSD ADC like the Grimm that you mentioned, only this time optimized for DSD at 5.6MHz.

 

Hmmm.. furthermore, if we could just have the raw multi-bit DS stream, it could even be kind of format agnostic. The end user could convert it to whatever suits his fancy. Keep it native, re-modulate to 1 bit DSD, decimate to DXD... whatever.

 

Ah... well, done dreaming now

 

Hey, there was a time when when all the cars, planes, mobile computers etc were just dreams in somebody's head.

 

Now that DSD has been decoupled from the physical carrier (SACD), it has opened up all kinds of opportunities for the DSD format. We have every right to dream BIG We can have 6-bit DSD stream or two-level analog at 5.6MHz or maybe even 11.2MHz.

[Hiro]

Too bad we can't store and playback the raw output from one of these multi-bit DS converters. Now THAT is something I would be interested in hearing. Pure multi-bit DS without all the intermediate filtering and re-modulations.

 

Think about a pure 1-bit (two-level analog) 5.6MHz DSD ADC with the fastest and most transparent high-end tubes etc designed by Eelco Grimm, Bruno Putzeys, Lukasz Fikus, Andreas Koch and Prof. Yoshio Yamasaki.

[Hiro]

Nothing prevents building such recorder both PCM4222 and the Arda chip have raw multi-bit modulator output.

 

The problem, however, is that no current delta-sigma DACs can handle such signal, except your DSC1, I believe.

[mlgrado]

The problem, however, is that no current delta-sigma DACs can handle such signal, except your DSC1, I believe.

 

 

And how would you transport it? Someone would need to fashion a custom driver for delivery over the common paths.

[Miska]

The problem, however, is that no current delta-sigma DACs can handle such signal, except your DSC1, I believe.

 

Yes, that's more of a problem.

 

DSC1 can accept up to "5-bit" (binary coded - IOW 32-bit unary coded (33-level)) SDM, all depending on how one pin is configured. By default it generates and decodes 32-bit unary (thermometer) coding itself from 1-bit input. Making the converter balanced would increase this to "6-bit".

 

But you can easily build suitable converters from DSD converter chips too (Wolfson or Cirrus Logic).

[Miska]

And how would you transport it? Someone would need to fashion a custom driver for delivery over the common paths.

 

It is quite easy to make such custom drivers for Linux. But also ASIO officially supports 8-bit SDM. I've been using just 8-bit bulk mode data transfers, so 6-bit needs to be zero-padded. For my personal use, Linux is all I need, it is anyway my primary development platform...

 

If you anyway use some USB MCU, then supporting 8-bit data transfers is most trivial thing you can do.

[mlgrado]

Yes, that's more of a problem.

 

DSC1 can accept up to "5-bit" (binary coded - IOW 32-bit unary coded (33-level)) SDM, all depending on how one pin is configured. By default it generates and decodes 32-bit unary (thermometer) coding itself from 1-bit input. Making the converter balanced would increase this to "6-bit".

 

But you can easily build suitable converters from DSD converter chips too (Wolfson or Cirrus Logic).

 

 

What you are doing is similar to what TI/Burr Brown does in its native DSD chips, right?

 

Also, a question that has been bugging me for some time.

 

Can you edit unary coded multi-bit delta sigma? As in, perform DSP on it? Volume control, etc? Since it is actually NOT like LPCM, in that it is really multiple 1-bit delta sigma streams in parallel.

 

I would think you would need to sum it to something that gives you more editing flexibility?

 

 

Thanks

[Miska]

What you are doing is similar to what TI/Burr Brown does in its native DSD chips, right?

 

All SDM D/A sections are more or less similar, main variation are in element weighting and data arrangement... "Discrete" converter like DSC1 can be configured to work in number of different ways.

 

Can you edit unary coded multi-bit delta sigma? As in, perform DSP on it? Volume control, etc? Since it is actually NOT like LPCM, in that it is really multiple 1-bit delta sigma streams in parallel.

 

Yes, definitely. It is more convenient format for certain operations. But as long as you stay in digital domain you can losslessly convert between unary, binary and other representations as you wish. The difference becomes only significant when you transform between analog and digital domains, because unary coding allows multiple representations for the same value as the symbol value drops.

 

Unary coded 4-bit value 1111 is equivalent of binary value 100 which is equivalent of decimal value 4. This one has only one representation in 4-bit unary space. However, if you look at decimal value 2 (binary 10) it has more combinations:

1010, 1100, 0011, 0101, 1001 and 0110

 

This is directly related to DAC linearity...

 

In PCM ladder DAC, as the level drops, less and less of the conversion elements are used and at LSB level only one. And elements cannot be used interchangeably, because each has certain weight relative to the bit position. Also precision requirements increase towards MSB bits (1/2^x). This causes quite a bit of non-linearities.

 

In SDM DAC, as the level drops, more and more bit combinations become possible and this allows increased linearity as the level drops. Because each bit (usually) has equal weight. So all conversion elements are fully utilized at all signal levels!

 

In DSC1 configured the default way, every input bit becomes converted by every conversion element once in a cycle. It is also moving average filter at the same time. Two benefits at once. (DEM and analog filter)

 

I would think you would need to sum it to something that gives you more editing flexibility?

 

If you sum two unary values 11 and 10 you get 1110. You multiple those, you get 1100. That is very simple operation. Just go on and derive other operations from this...

[mlgrado]

In DSC1 configured the default way, every input bit becomes converted by every conversion element once in a cycle. It is also moving average filter at the same time. Two benefits at once. (DEM and analog filter)

 

 

So, basically an analog FIR filter. It seems that in your DAC you have chosen to go for very flat frequency response, as opposed to others who allow more ultrasonics to pass?

 

 

 

If you sum two unary values 11 and 10 you get 1110. You multiple those, you get 1100. That is very simple operation. Just go on and derive other operations from this...

 

Sorry, but the math is admittedly over my head I barely passed algebra. lol

 

But just for the sake of clarity, you are saying you can DIRECTLY edit a multi-bit delta sigma stream as it is? No filtering or summation or 'intermediary' format?

 

Also, when converting from multi-bit delta sigma to 1 bit, can you directly apply the multi-bit SDM stream to a modulator and get 1 bit? My typical understanding is that you can't or don't send an already modulated signal into a modulator, regardless of bits. An intermediary format is required. But I could be very wrong... hence my question...

 

One last question, sorry! When you do need an intermediary format for editing delta sigma, for instance, DSD, is this intermediary (typically derived from a FIR filter or similar) Linear PCM, Differential PCM, Sigma DPCM? The descriptions I have heard used talk about encoding the 'difference' between samples. That sounds more specifically like DPCM to me, which is a form of Delta Modulation... not QUITE delta-sigma, but certainly related.

 

 

Thanks so much for your time!! Happy listening!!!

 

A.

[Hiro]

In PCM ladder DAC, as the level drops, less and less of the conversion elements are used and at LSB level only one. And elements cannot be used interchangeably, because each has certain weight relative to the bit position. Also precision requirements increase towards MSB bits (1/2^x). This causes quite a bit of non-linearities.

 

I remember reading similar reasons at dCS website for their abandonment of PCM.

[Miska]

So, basically an analog FIR filter. It seems that in your DAC you have chosen to go for very flat frequency response, as opposed to others who allow more ultrasonics to pass?

 

Yes, analog FIR being one aspect of it. There are many reasons for the way it is...

 

But just for the sake of clarity, you are saying you can DIRECTLY edit a multi-bit delta sigma stream as it is? No filtering or summation or 'intermediary' format?

 

You can do anything you like with it... You just need about two orders of magnitude more processing power. But so what, Moore's law already fixed it...

 

My typical understanding is that you can't or don't send an already modulated signal into a modulator, regardless of bits.

 

You may want to look at MASH modulator architecture, it generates N output bits from M input bits by number of cascaded 1st order modulators.

 

And ESS' HyperStream is something I'd call "MASH on steroids".

 

One last question, sorry! When you do need an intermediary format for editing delta sigma, for instance, DSD, is this intermediary (typically derived from a FIR filter or similar) Linear PCM, Differential PCM, Sigma DPCM? The descriptions I have heard used talk about encoding the 'difference' between samples. That sounds more specifically like DPCM to me, which is a form of Delta Modulation... not QUITE delta-sigma, but certainly related.

 

It depends on who is doing and what, it may not be any of the above. But it doesn't need to have the PCM three letter abbreviation on it. And you can have multiple bits in different ways, you can have multiple bits in parallel, multiple bits in time, or any combination of the two...

 

PCM is not any better for processing (and I disregard computational loads as unimportant now), although some think it is.

- If you add two 24-bit values, you get 25-bit result and the operation is not bit-perfect

- If you multiply two 24-bit values, you get 48-bit result and the operation is not bit-perfect

- If you want to output result from above in 24-bit format, you have inevitable loss of precision and you have to deal with it, usually by dithering (so it is not bit-perfect)

 

SDM processing at least partially solves these. For the third point, it is hard to increase true precision of PCM ladder DAC (number of bits), while it is much easier to increase SDM output rate and solve the problem. If you double SDM output rate while doing processing, you double the usable bandwidth and you increase available dynamic range within the usable bandwidth substantially.

[mlgrado]

Yes, analog FIR being one aspect of it. There are many reasons for the way it is...

 

 

 

You can do anything you like with it... You just need about two orders of magnitude more processing power. But so what, Moore's law already fixed it...

 

 

 

You may want to look at MASH modulator architecture, it generates N output bits from M input bits by number of cascaded 1st order modulators.

 

And ESS' HyperStream is something I'd call "MASH on steroids".

 

 

 

It depends on who is doing and what, it may not be any of the above. But it doesn't need to have the PCM three letter abbreviation on it. And you can have multiple bits in different ways, you can have multiple bits in parallel, multiple bits in time, or any combination of the two...

 

PCM is not any better for processing (and I disregard computational loads as unimportant now), although some think it is.

- If you add two 24-bit values, you get 25-bit result and the operation is not bit-perfect

- If you multiply two 24-bit values, you get 48-bit result and the operation is not bit-perfect

- If you want to output result from above in 24-bit format, you have inevitable loss of precision and you have to deal with it, usually by dithering (so it is not bit-perfect)

 

SDM processing at least partially solves these. For the third point, it is hard to increase true precision of PCM ladder DAC (number of bits), while it is much easier to increase SDM output rate and solve the problem. If you double SDM output rate while doing processing, you double the usable bandwidth and you increase available dynamic range within the usable bandwidth substantially.

 

 

Ok. That clarifies some things. I think.

 

As long as you have something more than 1 bit to work with, you can send it into the modulator. This includes multiple-bit delta sigma.

 

Now as far as DSD, that presents a problem. If you want to oversample, undersample, do any DSP, you need to make it multi-bit first. Then you re-modulate back to 1 bit. Or whatever suits your purpose.

 

This multi-bit representation can be many things. I went down a list, and you say it could even be none of those. Whatever it may be. You guys that code these things and do the math, I will trust you.

 

I don't know why we have made the three letters PCM so evil. PCM doesn't mean Linear, twos compliment PCM in every case.

DPCM is a totally different animal. So is Sigma DPCM (multi-bit delta sigma). Some of these codings are differential. Some are absolute value. Some may be neither. I don't know.

 

Here is an example of an FIR filter applied to DSD. As best as I can tell, the author of the code says it converts to DPCM at the same sample rate for processing.

 

DSD (SACD) FIR based software crossover - diyAudio

 

 

DSD-wide also uses an FIR filter to sum DSD into 8 bit words at same sample rate. Based on the low bit rate, I assume we are talking about some kind of differential coding as well.

 

 

That said, I don't really care about what the intermediate format is, as long as it sounds good in the end result. I will say that the filtering itself concerns me. Although it may not be decimating the sample rate, filtering still can leave its mark on the sound. Impulse response issues, ringing, etc. are not exclusive to decimation filtering. For instance, the impulse response of the FIR filter used to create DSD-wide is around 96khz. Honestly, that isn't really all that much different than what you might expect with decimation.

 

 

In the end, I don't want anyone to mistake what I am saying as lack of enthusiasm for DSD. Hardly. I LOVE it. My favorite recordings are in DSD. I love the work the guys at Channel Classics and others are doing for the format. I am concerned, though, about the effect of filtering and processing on the DSD signal. I am a 'pure' DSD kind of guy, who likes to convert it as is with nothing more than a single, simple FIR analog filtering.

 

I am INTRIGUED by your work, Miska, with DSD. I try to understand it as best I can. Like I said, I prefer no processing, but I understand also that processing if done correctly isn't a bad thing at all. It is all in the implementation. Just trying to understand more about it.

 

 

A.